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sbas274e ? march 2003 ? revised june 2004 features data rate: 5msps (10msps in 2x mode) signal-to-noise ratio: 88db total harmonic distortion: ?99db spurious-free dynamic range: 101db linear phase with 2.45 mhz bandwidth passband ripple: 0.0025db selectable on-chip reference directly connects to tms320c6000 dsps easily upgradable to 18 bits with the ads1625 and ads1626 adjustable power dissipation: 315 to 570mw power down mode supplies: analog +5v digital +3v digital i/o +2.7 to +5.25v applications scientific instruments automated test equipment data acquisition medical imaging vibration analysis description the ADS1605 and ads1606 are high-speed, high-precision, delta-sigma analog-to-digital converters (adcs) with 16-bit resolution. the data rate is 5 mega-samples per second (msps), the b andwidth (?3db) is 2.45mhz, and passband ripple is less than 0.0025db (to 2.2mhz). both devices offer the same outstanding performance at these speeds with a signal-to-noise ratio up to 88db, total harmonic distortion down to ?99db, and a spurious-free dynamic range up to 101db. for even higher-speed operation, the data rate can be doubled to 10msps in 2x mode. the ads1606 includes an adjustable first-in first-out buffer (fifo) for the output data. the input signal is measured against a voltage reference that can be generated on-chip or supplied externally. the digital output data is provided over a simple parallel interface that easily connects to digital signal processors (dsps). an out-of-range monitor reports when the input range has been exceeded. the ADS1605/6 operate from a +5v analog supply (avdd) and +3v digital supply (dvdd). the digital i/o supply (iovdd) operates from +2.7 to +5.25v, enabling the digital interface to support a range of logic families. the analog power dissipation is set by an external resistor and can be reduced when operating at slower speeds. a power down mode, activated by a digital i/o pin, shuts down all circuitry. the ADS1605/6 are offered in a tqfp-64 package using ti powerpad ? technology. the ADS1605 and ads1606, along with their 18-bit counterparts, the ads1625 and ads1626, are well suited for the demanding measurement requirements of scientific instrumentation, automated test equipment, data acquisi- tion, and medical imaging. refen fifo_lev[2:0] dout[15:0] otr drdy rd 2xmode cs clk pd reset ads1606 only fifo i/o interface digital filter modulator reference and bias circuits dgnd agnd avdd dvdd iovdd vcap rbias vmid vrefn vrefp ainp ainn ADS1605 ads1606 powerpad is a trademark of texas instruments. all other trademarks are the property of their respective owners. www.ti.com copyright ? 2003?2004, t exas instruments incorporated please be aware that an important notice concerning availability, standard warranty, and use in critical applications of t exas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
sbas274e ? march 2003 ? revised june 2004 www.ti.com 2 ordering information product package?lead package designator (1) specified temperature range package marking ordering number transport media, quantity ADS1605 tqfp?64 pap ?40 c to +85 c ADS1605i ADS1605ipapt tape and reel, 250 ADS1605 tqfp?64 powerpad pap ?40 c to +85 c ADS1605i ADS1605ipapr tape and reel, 1000 ads1606 tqfp?64 pap ?40 c to +85 c ads1606i ads1606ipapt tape and reel, 250 ads1606 tqfp?64 powerpad pap ?40 c to +85 c ads1606i ads1606ipapr tape and reel, 1000 (1) for the most current specification and package information, refer to our web site at www .ti.com. absolute maximum ratings over operating f ree-air temperature range unless otherwise noted (1) ADS1605, ads1606 unit avdd to agnd ?0.3 to +6 v dvdd to dgnd ?0.3 to +3.6 v iovdd to dgnd ?0.3 to +6 v agnd to dgnd ?0.3 to +0.3 v input current 100ma, momentary input current 10ma, continuous analog i/o to agnd ?0.3 to avdd + 0.3 v digital i/o to dgnd ?0.3 to iovdd + 0.3 v maximum junction t emperature +150 c operating temperature range ?40 to +105 c storage temperature range ?60 to +150 c lead temperature (soldering, 10s) +260 c (1) stresses above these ratings may cause permanent damage. exposure to absolute maximum conditions for extended periods may degrade device reliability. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. product family product resolution data rate fifo? ADS1605 16 bits 5.0msps no ads1606 16 bits 5.0msps yes ads1625 18 bits 1.25msps no ads1626 18 bits 1.25msps yes this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
sbas274e ? march 2003 ? revised june 2004 www.ti.com 3 electrical characteristics all specifications at ?40 c to +85 c, avdd = 5v, dvdd = iovdd = 3v, f clk = 40mhz, external v ref = +3v, 2xmode = low, v cm = 2.0v, fifo disabled, and r bias = 37k ? , unless otherwise noted. parameter test conditions min typ max unit analog input 0dbfs 1.545v ref v differential input voltage (v in ) (ainp ? ainn) ?2dbfs 1.227v ref v differential input voltage (v in ) (ainp ? ainn) ?6dbfs 0.774v ref v ?20dbfs 0.155v ref v common-mode input voltage (v cm ) (ainp + ainn) / 2 2.0 v absolute input voltage (ainp or ainn with respect to agnd) 0dbfs ?0.1 4.7 v absolute input voltage (ainp or ainn with respect to agnd) ?2dbfs input and smaller 0.1 4.2 v dynamic specifications data rate 5.0 f clk 40 mhz msps f in = 100khz, ?2dbfs 88 db f in = 100khz, ?6dbfs 84 db f in = 100khz, ?20dbfs 62 70 db f in = 500khz, ?2dbfs 86 db signal?to?noise ratio (snr) f in = 500khz, ?6dbfs 83 db signal?to?noise ratio (snr) f in = 500khz, ?20dbfs 69 db f in = 2mhz, ?2dbfs 84 db f in = 2mhz, ?6dbfs 82 db f in = 2mhz, ?20dbfs 69 db f in = 100khz, ?2dbfs ?93 db f in = 100khz, ?6dbfs ?99 db f in = 100khz, ?20dbfs ?94 ?85 db f in = 500khz, ?2dbfs ?94 db total harmonic distortion (thd) f in = 500khz, ?6dbfs ?97 db total harmonic distortion (thd) f in = 500khz, ?20dbfs ?93 db f in = 2mhz, ?2dbfs ?98 db f in = 2mhz, ?6dbfs ?101 db f in = 2mhz, ?20dbfs ?92 db f in = 100khz, ?2dbfs 86 db f in = 100khz, ?6dbfs 84 db f in = 100khz, ?20dbfs 62 70 db f in = 500khz, ?2dbfs 86 db signal?to?noise and distortion (sinad) f in = 500khz, ?6dbfs 83 db signal?to?noise and distortion (sinad) f in = 500khz, ?20dbfs 69 db f in = 2mhz, ?2dbfs 84 db f in = 2mhz, ?6dbfs 82 db f in = 2mhz, ?20dbfs 69 db
sbas274e ? march 2003 ? revised june 2004 www.ti.com 4 electrical characteristics (continued) all specifications at ?40 c to +85 c, avdd = 5v, dvdd = iovdd = 3v, f clk = 40mhz, external v ref = +3v, 2xmode = low, v cm = 2.0v, fifo disabled, and r bias = 37k ? , unless otherwise noted. parameter unit max typ min test conditions f in = 100khz, ?2dbfs 96 db f in = 100khz, ?6dbfs 101 db f in = 100khz, ?20dbfs 85 96 db f in = 500khz, ?2dbfs 95 db spurious free dynamic range (sfdr) f in = 500khz, ?6dbfs 100 db spurious free dynamic range (sfdr) f in = 500khz, ?20dbfs 95 db f in = 2mhz, ?2dbfs 102 db f in = 2mhz, ?6dbfs 105 db f in = 2mhz, ?20dbfs 96 db intermodulation distortion (imd) f 1 = 1.99mhz, ?6dbfs f = 2.00mhz, ?6dbfs ?94 db intermodulation distortion (imd) f 1 = 1.99mhz, ?6dbfs f 2 = 2.00mhz, ?6dbfs ?94 db aperture delay 4 ns digital filter characteristics pass band 0 2.2 f clk 40 mhz mhz pass band ripple 0.0025 db pass band transition ?0.1db attenuation 2.3 f clk 40 mhz mhz pass band transition ?3.0db attenuation 2.45 f clk 40 mhz mhz stop band 2.8 f clk 40 mhz 37.2 f clk 40 mhz mhz stop band attenuation 72 db group delay 5.2 40 mhz f clk s settling time to 0.001% 9.4 40 mhz f clk s static specifications resolution 16 bits no missing codes 16 bits input referred noise 1.0 lsb, rms integral nonlinearity ?1.5dbfs signal 0.75 lsb differential nonlinearity 0.25 lsb offset error 0.05 %fsr offset error drift 1 ppmfsr/ c gain error 0.25 % gain error drift excluding reference drift 10 ppm/ c common-mode rejection at dc 75 db power-supply rejection at dc 65 db
sbas274e ? march 2003 ? revised june 2004 www.ti.com 5 electrical characteristics (continued) all specifications at ?40 c to +85 c, avdd = 5v, dvdd = iovdd = 3v, f clk = 40mhz, external v ref = +3v, 2xmode = low, v cm = 2.0v, fifo disabled, and r bias = 37k ? , unless otherwise noted. parameter unit max typ min test conditions voltage reference (1) v ref = (vrefp ? vrefn) 2.5 3.0 3.2 v vrefp 3.75 4.0 4.25 v vrefn 0.75 1.0 1.25 v vmid 2.3 2.5 2.8 v v ref drift internal reference (refen = low) 50 ppm/ c startup time internal reference (refen = low) 15 ms clock input frequency (f clk ) 40 50 mhz duty cycle f clk = 40mhz 45 55 % digital input/output v ih 0.7 iovdd iovdd v v il dgnd 0.3 iovdd v v oh i oh = 50 a iovdd ? 0.5 v v ol i ol = 50 a dgnd +0.5 v input leakage dgnd < v digin < iovdd 10 a power-supply requirements avdd 4.75 5.25 v dvdd 2.7 3.3 v iovdd 2.7 5.25 v avdd current (i avdd ) refen = low 110 135 ma avdd current (i avdd ) refen = high 85 105 ma dvdd current (i dvdd ) 45 55 ma iovdd current (i iovdd ) iovdd = 3v 4 6 ma power dissipation avdd = 5v, dvdd = 3v, iovdd = 3v, refen = high 570 710 mw power dissipation pd = low, clk disabled 5 mw temperature range specified ?40 +85 c operating ?40 +105 c storage ?60 +150 c thermal resistance, ja powerpad ? soldered to pcb with 2oz. trace and copper pad. 25 c/w jc powerpad soldered to pcb with 2oz. trace and copper pad. 0.5 c/w (1) the specification limits for vref, vrefp, vrefn, and vmid apply when using the internal or an external reference. the internal reference voltages are bounded by the limits shown. when using an external reference, the limits indicate the allowable voltages that can be applied to the reference pins.
sbas274e ? march 2003 ? revised june 2004 www.ti.com 6 definitions absolute input voltage absolute input voltage, given in volts, is the voltage of each analog input (ainn or ainp) with respect to agnd. aperture delay aperture delay is the delay between the rising edge of clk and the sampling of the input signal. common-mode input voltage common-mode input voltage (v cm ) is the average voltage of the analog inputs: (ainp ainn) 2 differential input voltage differential input voltage (v in ) is the voltage difference between the analog inputs: (ainp?ainn). differential nonlinearity (dnl) dnl, given in least-significant bits of the output code (lsb), is the maximum deviation of the output code step sizes from the ideal value of 1lsb. full-scale range (fsr) fsr is the dif ference between the maximum and minimum measurable input signals. fsr = 2 1.545v ref . gain error gain error, given in %, is the error of the full-scale input signal with respect to the ideal value. gain error drift gain error drift, given in ppm/ c, is the drift over temperature of the gain error. the gain error is specified as the larger of the drift from ambient (t = 25 c) to the minimum or maximum operating temperatures. integral nonlinearity (inl) inl, given in least-significant bits of the output code (lsb), is the maximum deviation of the output codes from a best fit line. intermodulation distortion (imd) imd, given in db, is measured while applying two input signals of the same magnitude, but with slightly different frequencies. it is calculated as the difference between the rms amplitude of the input signal to the rms amplitude of the peak spurious signal. offset error offset error, given in % of fsr, is the output reading when the differential input is zero. offset error drift offset error drift, given in ppm of fsr/ c, is the drift over temperature of the of fset error. the of fset error is specified as the larger of the drift from ambient (t = 25 c) to the minimum or maximum operating temperatures. signal-to-noise ratio (snr) snr, given in db, is the ratio of the rms value of the input signal to the sum of all the frequency components below f clk /2 (the nyquist frequency) excluding the first six harmonics of the input signal and the dc component. signal-to-noise and distortion (sinad) sinad, given in db, is the ratio of the rms value of the input signal to the sum of all the frequency components below f clk /2 (the nyquist frequency) including the harmonics of the input signal but excluding the dc component. spurious free dynamic range (sfdr) sfdr, given in db, is the difference between the rms amplitude of the input signal to the rms amplitude of the peak spurious signal. total harmonic distortion (thd) thd, given in db, is the ratio of the sum of the rms value of the first six harmonics of the input signal to the rms value of the input signal.
sbas274e ? march 2003 ? revised june 2004 www.ti.com 7 pin assignments tqfp package (top view) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 fifo_lev[2] (ads1606 only) fifo_lev[1] (ads1606 only) fifo_lev[0] (ads1606 only) nc dout[15] dout[14] dout[13] dout[12] dout[11] dout[10] dout[9] dout[8] dout[7] dout[6] dout[5] dout[4] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 agnd avdd agnd ainn ainp agnd avdd rbias agnd avdd agnd avdd refen nc 2xmode nc vrefp vrefp vmid vrefn vrefn vcap avdd agnd clk agnd dgnd iovdd dvdd dgnd nc nc pd dvdd dgnd reset cs rd otr drdy dgnd dvdd nc nc dout[0] dout[1] dout[2] dout[3] 64 63 62 61 60 59 58 57 56 55 54 17 18 19 20 21 22 23 24 25 26 27 53 52 51 50 49 28 29 30 31 32 ADS1605 ads1606 powerpad tm terminal functions terminal type description name no. type description agnd 1, 3, 6, 9, 11, 55, 57 analog analog ground avdd 2, 7, 10, 12, 58 analog analog supply ainn 4 analog input negative analog input ainp 5 analog input positive analog input rbias 8 analog terminal for external analog bias setting resistor refen 13 digital input: active low internal reference enable. internal pull-down resistor of 170k ? to dgnd. nc 14,16, 27, 28, 45, 50 not connected these terminals are not connected within the ADS1605/6 and must be left unconnected. 2xmode 15 digital input digital filter decimation rate. internal pull-down resistor of 170k ? to dgnd. pd 17 digital input: active low power down all circuitry. internal pull-up resistor of 170k ? to dgnd. dvdd 18, 26, 52 digital digital supply dgnd 19, 25, 51, 54 digital digital ground reset 20 digital input: active low reset digital filter cs 21 digital input: active low chip select rd 22 digital input: active low read enable otr 23 digital output analog inputs out of range drdy 24 digital output: active low data ready on falling edge dout [15:0] 29?44 digital output data output. dout[15] is the msb and dout[0] is the lsb. fifo_lev[2:0] 46?48 digital input fifo level (for the ads1606 only). fifo_lev[2] is msb. note: these terminals must be left disconnected on the ADS1605. iovdd 53 digital digital i/o supply clk 56 digital input clock input vcap 59 analog terminal for external bypass capacitor connection to internal bias voltage vrefn 60, 61 analog negative reference voltage vmid 62 analog midpoint voltage vrefp 63, 64 analog positive reference voltage
sbas274e ? march 2003 ? revised june 2004 www.ti.com 8 parameter measurement information drdy clk dout[15:0] data n + 1 t 1 t 2 t 2 t 3 t 5 t 6 t 4 t 4 data n data n + 2 note: cs and rd tied low. figure 1. data retrieval timing (ADS1605, ads1606 with fifo disabled) rd, cs dout[15:0] t 8 t 7 figure 2. dout inactive/active timing (ADS1605, ads1606 with fifo disabled) timing requirements for figures 1 and 2 symbol description min typ max unit t 1 clk period (1/f clk ) 20 25 1000 ns 1/t 1 f clk 1 40 50 mhz t 2 clk pulse width, high or low 10 ns t 3 rising edge of clk to drdy low 10 ns t 4 drdy pulse width high or low 4 t 1 ns t 5 falling edge of drdy to data invalid 10 ns t 6 falling edge of drdy to data valid 15 ns t 7 rising edge of rd and/or cs inactive (high) to dout high impedance 15 ns t 8 falling edge of rd and/or cs active (low) to dout active. 15 ns note: dout[15:0] and drdy load = 10pf.
sbas274e ? march 2003 ? revised june 2004 www.ti.com 9 clk reset drdy dout[15:0] t 10 t 9 t 12 t 3 t 11 settled data note: cs and rd tied low. figure 3. reset timing (ADS1605, ads1606 with fifo disabled) timing requirements for figure 3 symbol description min typ max unit t 3 rising edge of clk to drdy low 10 ns t 9 reset pulse width 50 ns t 10 delay from reset active (low) to drdy forced high and dout forced low 9 ns t 11 reset rising edge to falling edge of clk ?5 10 ns t 12 delay from dout active to valid dout (settling to 0.001%) 47 drdy cycles note: dout[15:0] and drdy load = 10pf.
sbas274e ? march 2003 ? revised june 2004 www.ti.com 10 clk drdy dout[15:0] d1 d2 dl (2) t 2 t 2 t 16 t 17 t 21 t 15 t 20 t 18 t 19 t 1 t 13 t 14 cs (1 ) r d (1) cs may be tied low. (2) the number of data readings (dl) is set by the fifo level. figure 4. data retrieval timing (ads1606 with fifo enabled) rd, cs dout[15:0] t 8 t 7 figure 5. dout inactive/active timing (ads1606 with fifo enabled) timing requirements for figure 4 and figure 5 symbol description min typ max unit t 1 clk period (1/f clk ) 20 25 1000 ns t 2 clk pulse width, high or low 10 ns t 7 rising edge of rd and/or cs inactive (high) to dout high impedance 7 15 ns t 8 falling edge of rd and/or cs active (low) to dout active. 7 15 ns t 13 rising edge of clk to drdy high 12 ns t 14 drdy period 8 fifo level (1) clk cycles t 15 drdy positive pulse width 1 clk cycles t 16 rd high hold time after drdy goes low 0 ns t 17 cs low before rd goes low 0 ns t 18 rd negative pulse width 10 ns t 19 rd positive pulse width 10 ns t 20 rd high before drdy toggles 2 clk cycles t 21 rd high before cs goes high 0 ns note: dout[15:0] and drdy load = 10pf. (1) see fifo section for more details.
sbas274e ? march 2003 ? revised june 2004 www.ti.com 11 clk reset t 11 t 23 t 24 t 25 t 26 t 9 drdy r d figure 6. reset timing (ads1606 with fifo enabled) timing requirements for figure 6 symbol description min typ max unit t 9 reset pulse width 50 ns t 11 reset rising edge to falling edge of clk ?5 10 ns t 23 rd pulse low after reset goes high 8 clk cycles t 24 rd pulse high before first drdy pulse after reset goes high 8 clk cycles t 25 drdy low after reset goes low 8 (fifo level + 1) clk cycles t 26 delay from reset high to valid dout (settling to 0.001%) see table 4 drdy cycles
sbas274e ? march 2003 ? revised june 2004 www.ti.com 12 typical characteristics all specifications at t a = 25 c, avdd = 5v, dvdd = iovdd = 3v, f clk = 40mhz, external v ref = +3v, 2xmode = low, v cm = 2.0v, and r bias = 37k ? , unless otherwise noted. spectral response 0 0.5 1.0 1.5 2.0 2.5 frequency (mhz) amplitude (db) 0 ? 20 ? 40 ? 60 ? 80 ? 100 ? 120 ? 140 ? 160 f in =100khz, ? 2dbfs snr = 88db thd = ? 93db sfdr = 96db spectral response 0 0.5 1.0 1.5 2.0 2.5 frequency (mhz) amplitude (db) 0 ? 20 ? 40 ? 60 ? 80 ? 100 ? 120 ? 140 ? 160 f in =100khz, ? 6dbfs snr = 84db thd = ? 99db sfdr = 101db spectral response 0 0.5 1.0 1.5 2.0 2.5 frequency (mhz) amplitude (db) 0 ? 20 ? 40 ? 60 ? 80 ? 100 ? 120 ? 140 ? 160 f in = 500khz, ? 2dbfs snr = 86db thd = ? 97db sfdr = 97db spectral response 0 0.5 1.0 1.5 2.0 2.5 frequency (mhz) amplitude (db) 0 ? 20 ? 40 ? 60 ? 80 ? 100 ? 120 ? 140 ? 160 f in =500khz, ? 6dbfs snr = 83db thd = ? 103db sfdr = 106db spectral response 0 0.5 1.0 1.5 2.0 2.5 frequency (mhz) amplitude (db) 0 ? 20 ? 40 ? 60 ? 80 ? 100 ? 120 ? 140 ? 160 f in =2mhz, ? 2dbfs snr = 84db thd = ? 98db sfdr = 102db spectral response 0 0.5 1.0 1.5 2.0 2.5 frequency (mhz) amplitude (db) 0 ? 20 ? 40 ? 60 ? 80 ? 100 ? 120 ? 140 ? 160 f in =2mhz, ? 6dbfs snr = 82db thd = ? 101db sfdr = 105db
sbas274e ? march 2003 ? revised june 2004 www.ti.com 13 typical characteristics (continued) all specifications at t a = 25 c, avdd = 5v, dvdd = iovdd = 3v, f clk = 40mhz, external v ref = +3v, 2xmode = low, v cm = 2.0v, and r bias = 37k ? , unless otherwise noted. 18k 16k 14k 12k 10k 8k 6k 4k 2k 0 occurrences ? 5 ? 4 ? 3 ? 2 ? 1012345 output code (lsb) noise histogram v in =0v 0 ? 20 ? 40 ? 60 ? 80 ? 100 ? 120 ? 140 ? 160 power spectral density (db) frequency (mhz) intermodulation response 1.95 1.96 1.97 1.98 1.99 2.00 2.01 2.02 2.03 2.04 2.05 f in1 =1.99mhz f in2 =2.00mhz imd = ? 94db signal?to? noise ratio, total harmonic distortion, and spurious? free dynamic range vs input signal amplitude ? 70 ? 60 ? 50 ? 40 ? 30 ? 20 ? 10 0 input signal amplitude, v in (db) snr, thd, and sfdr (db) 110 100 90 80 70 60 50 40 30 20 10 sfdr thd snr f in = 100khz signal? to?noise ratio vs input frequency 0.001 0.01 0.1 1 10 input frequency, f in (mhz) snr (db) 90 85 80 75 70 65 60 v in = ? 2dbfs v in = ? 6dbfs v in = ? 20dbfs total harmonic distortion vs input frequency 0.001 0.01 0.1 1 10 input frequency, f in (mhz) thd (db) ? 85 ? 90 ? 95 ? 100 ? 105 ? 11 0 v in = ? 6dbfs v in = ? 2dbfs v in = ? 20dbfs spurious?free dynamic range vs input frequency 0.001 0.01 0.1 1 10 input frequency, f in (mhz) sfdr (db) 110 108 106 104 102 100 98 96 94 92 90 v in = ? 6dbfs v in = ? 2dbfs v in = ? 20dbfs
sbas274e ? march 2003 ? revised june 2004 www.ti.com 14 typical characteristics (continued) all specifications at t a = 25 c, avdd = 5v, dvdd = iovdd = 3v, f clk = 40mhz, external v ref = +3v, 2xmode = low, v cm = 2.0v, and r bias = 37k ? , unless otherwise noted. signal?to?noise ratio vs input common?mode voltage 1.5 1.9 1.7 2.1 2.3 2.5 input common? mode voltage, v cm (v) snr (db) 89 87 85 83 81 79 77 75 v in = ? 6dbfs v in = ? 2dbfs f in = 100khz total harmonic distortion vs input common?mode voltage 1.5 1.9 1.7 2.1 2.3 2.5 input common? mode voltage, v cm (v) thd (db) ? 65 ? 75 ? 85 ? 95 ? 105 ? 11 5 ? 125 ? 135 v in = ? 6dbfs v in = ? 2dbfs f in = 100khz spurious?free dynamic range vs input common?mode voltage 1.5 1.9 1.7 2.1 2.3 2.5 input common?mode voltage, v cm (v) sfdr (db) 105 100 95 90 85 80 75 70 65 v in = ? 6dbfs v in = ? 2dbfs f in = 100khz signal?to? noise ratio vs clk frequency 10 30 20 40 50 60 snr (db) 90 85 80 75 70 65 60 55 50 45 40 f in = 100khz, 6dbfs r bias =60k ? r bias = 30k ? r bias = 50k ? r bias = 45k ? r bias =37k ? clk frequency, f clk (mhz) total harmonic distortion vs clk frequency 10 30 20 40 50 60 thd (db) ? 65 ? 70 ? 75 ? 80 ? 85 ? 90 ? 95 ? 100 ? 105 f in = 100khz, ? 6dbfs clk frequency, f clk (mhz) r bias =60k ? r bias =37k ? r bias = 30k ? r bias =50k ? r bias =45k ? spurious?free dynamic range vs clk frequency 10 30 20 40 50 60 sfdr (db) 11 0 105 100 95 90 85 80 75 f in =100khz, ? 6dbfs clk frequency, f clk (mhz) r bias = 45k ? r bias = 50k ? r bias = 60k ? r bias =30k ? r bias =37k ?
sbas274e ? march 2003 ? revised june 2004 www.ti.com 15 typical characteristics (continued) all specifications at t a = 25 c, avdd = 5v, dvdd = iovdd = 3v, f clk = 40mhz, external v ref = +3v, 2xmode = low, v cm = 2.0v, and r bias = 37k ? , unless otherwise noted. signal?to?noise ratio vs temperature temperature ( c) ? 40 10 ? 15 35 60 85 snr (db) 100 90 80 70 60 50 v in = ? 6dbfs v in = ? 2dbfs v in = ? 20dbfs f in = 100khz total harmonic distortion vs temperature temperature ( c) ? 40 10 ? 15 35 60 85 thd (db) ? 85 ? 90 ? 95 ? 100 ? 105 ? 11 0 v in = ? 6dbfs v in = ? 2dbfs v in = ? 20dbfs f in =100khz spurious?free dynamic range vs temperature temperature ( c) ? 40 10 ? 15 35 60 85 sfdr (db) 110 105 100 95 90 85 v in = ? 6dbfs v in = ? 2dbfs v in = ? 20dbfs f in =100khz power? supply current vs temperature temperature ( c) ? 40 10 ? 15 35 60 85 current (ma) 130 120 110 100 90 80 70 60 50 40 30 i avdd (refen = high) i avdd (refen = low) i dvdd +i iovdd dvdd = iovdd = 3v r bias = 37k ? ,f clk = 40mhz supply current vs clk frequency 20 10 30 40 50 clk frequency, f clk (mhz) supply current (ma) 100 80 60 40 20 0 avdd = 5v, dvdd = iovdd = 3v, refen = high i dvdd +i iovdd i avdd (r bias =37k ? ) i avdd (r bias = 60k ? ) analog supply current vs r bias r bias (k ? ) 35 30 40 45 50 55 60 analog current, i avdd (ma) 140 130 120 11 0 100 90 80 70 60 50 refen = low refen = high
sbas274e ? march 2003 ? revised june 2004 www.ti.com 16 typical characteristics (continued) all specifications at t a = 25 c, avdd = 5v, dvdd = iovdd = 3v, f clk = 40mhz, external v ref = +3v, 2xmode = low, v cm = 2.0v, and r bias = 37k ? , unless otherwise noted. integral nonlinearity 5k 10k 15k 20k 25k ? 25k ? 20k ? 15k ? 10k ? 5k 0 output code (lsb) inl (lsb) 1.0 0.8 0.6 0.4 0.2 0 ? 0.2 ? 0.4 ? 0.6 ? 0.8 ? 1.0 f in = 100hz, ? 1.5dbfs differential nonlinearity dnl (lsb) 0.5 0.4 0.3 0.2 0.1 0 ? 0.1 ? 0.2 ? 0.3 ? 0.4 ? 0.5 5k 10k 15k 20k 25k ? 25k ? 20k ? 15k ? 10k ? 5k 0 output code (lsb) f in =100hz, ? 1.5dbfs
sbas274e ? march 2003 ? revised june 2004 www.ti.com 17 overview the ADS1605 and ads1606 are high-performance delta-sigma adcs with a default oversampling ratio of 8. the modulator uses an inherently stable 2-1-1 pipelined delta-sigma modulator architecture incorporating proprietary circuitry that allows for very linear high-speed operation. the modulator samples the input signal at 40msps (when f clk = 40mhz). a low-ripple linear phase digital filter decimates the modulator output to provide data output word rates of 5msps with a signal passband out to 2.45mhz. the 2x mode, enabled by a digital i/o pin, doubles the data rate to 10msps by reducing the oversampling ratio to 4. see the 2x mode section for more details. conceptually, the modulator and digital filter measure the dif- ferential input signal, v in = (ainp ? ainn), against the scaled differential reference, v ref = (vrefp ? vrefn), as shown in figure 7. the voltage reference can either be generated internally or supplied externally. an 16-bit parallel data bus, designed for direct connection to dsps, outputs the data. a separate power supply for the i/o allows flexibility for interfac- ing to different logic families. out-of-range conditions are indi- cated with a dedicated digital output pin. analog power dis- sipation is controlled using an external resistor. this allows reduced dissipation when operating at slower speeds. when not in use, power consumption can be dramatically reduced using the pd pin. the ads1606 incorporates an adjustable fifo buffer for the output data. the level of the fifo is set by the fifo_lev[2:0] pins. other than the fifo buffer, the ADS1605 and ads1606 are identical, and are referred to to- gether in this data sheet as the ADS1605/6. analog inputs (ainp, ainn) the ADS1605/6 measures the differential signal, v in = (ainp ? ainn), against the differential reference, v ref = (vrefp ? vrefn). the reference is scaled internally so that the full-scale differential input voltage is 1.545v ref . that is, the most positive measurable differential input is 1.545v ref , which produces the most positive digital output code of 7fffh. likewise, the most negative measurable differential input is ?1.545v ref , which produces the most negative digital output code of 8000h. the ADS1605/6 supports a very wide range of input signals. for v ref = 3v, the full scale input voltages are 4.6v. having such a wide input range makes out-of-range signals unlikely. however, should an out-of-range signal occur, the digital output otr will go high. to achieve the highest analog performance, it is recommended that the inputs be limited to 1.227v ref (?2dbfs). for v ref = 3v, the corresponding recommended input range is 3.68v. the analog inputs must be driven with a differential signal to achieve optimum performance. the recommended common-mode voltage of the input signal, v cm ainp ainn 2 , is 2.0v. for signals larger than ?2dbfs, the input common-mode voltage needs to be raised in order to meet the absolute input voltage specifications. the typical characteristics show how performance varies with input common-mode voltage. in addition to the differential and common-mode input voltages, the absolute input voltage is also important. this is the voltage on either input (ainp or ainn) with respect to agnd. the range for this voltage is: 0.1v (ainn or ainp) 4.6v if either input is taken below ?0.1v, esd protection diodes on the inputs will turn on. exceeding 4.6v on either input will result in degradation in the linearity performance. esd protection diodes will also turn on if the inputs are taken above avdd (+5v). for signals below ?2dbfs, the recommended absolute input voltage is: 0.1v (ainn or ainp) 4.2v keeping the inputs within this range provides for optimum performance. ? modulator digital filter parallel interface 1.545v ref 1.545 v ref v in vrefn iovdd vrefp ainp ainn otr 2xmode fifo_lev[2:0] dout[15:0] ads1606 only fifo figure 7. conceptual block diagram
sbas274e ? march 2003 ? revised june 2004 www.ti.com 18 input circuitry the ADS1605/6 uses switched-capacitor circuitry to measure the input voltage. internal capacitors are charged by the inputs and then discharged internally with this cycle repeating at the frequency of clk. figure 8 shows a conceptual diagram of these circuits. switches s2 represent the net effect of the modulator circuitry in discharging the sampling capacitors, the actual implementation is different. the timing for switches s1 and s2 is shown in figure 9. s 1 s 2 10pf ainp ADS1605 ads1606 8pf vmid s 1 s 2 10pf ainn 8pf vmid agnd figure 8. conceptual diagram of internal circuitry connected to the analog inputs on s1 s2 off on off t sample =1/f clk figure 9. timing for the switches in figure 2 driving the inputs the external circuits driving the ADS1605/6 inputs must be able to handle the load presented by the switching capacitors within the ADS1605/6. the input switches s1 in figure 5 are closed approximately one half of the sampling period, t sample , allowing only 12ns for the internal capacitors to be charged by the inputs, when f clk = 40mhz. figure 10 and figure 11 show the recommended circuits when using single-ended or differential op amps, respectively. the analog inputs must be driven differentially to achieve optimum performance. the external capacitors, between the inputs and from each input to agnd, improve linearity and should be placed as close to the pins as possible. place the drivers close to the inputs and use good capacitor bypass techniques on their supplies; usually a smaller high-quality ceramic capacitor in parallel with a larger capacitor. keep the resistances used in the driver circuits low?thermal noise in the driver circuits degr ades the overall noise performance. when the signal can be ac-coupled to the ADS1605/6 inputs, a simple rc filter can set the input common mode voltage. the ADS1605/6 is a high-speed, high?performance adc. special care must be taken when selecting the test equipment and setup used with this device. pay particular attention to the signal sources to ensure they do not limit performance when measuring the ADS1605/6. 392 ? opa2822 ADS1605 ads1606 agnd opa2822 40pf v cm (1) v cm (1) v cm (1) 100pf ainp ainn 100pf (3) 392 ? 40pf 100pf (1) recommended v cm =2.0v. (2) optional ac?coupling circuit provides common?mode input voltage. (3) increase to 390pf when f in 100khz for improved snr and thd. (2) (2) (2) (2) ? v in 2 v in 2 392 ? 392 ? 392 ? 0.01 f 0.01 f 392 ? 1 f 392 ? 1k ? 1k ? 1 f 392 ? 49.9 ? 49.9 ? figure 10. recommended driver circuit using the opa2822 ADS1605 ths4503 ads1606 22pf ? v in +v in 100pf 100pf ainp ainn 100pf 24.9 ? 392 ? 392 ? 24.9 ? 392 ? 392 ? 22pf v cm figure 11. recommended driver circuits using the ths4503 differential amplifier
sbas274e ? march 2003 ? revised june 2004 www.ti.com 19 reference inputs (vrefn, vrefp, vmid) the ADS1605/6 can operate from an internal or external voltage reference. in either case, the reference voltage v ref is set by the differential voltage between vrefn and vrefp: v ref = (vrefp ? vrefn). vrefp and vrefn each use two pins, which should be shorted together. vmid equals approximately 2.5v and is used by the modulator. vcap connects to an internal node and must also be bypassed with an external capacitor. for the best analog performance, it is recommended that an external reference voltage (v ref ) of 3.0v be used. internal reference (refen = low) to use the internal reference, set the refen pin low. this activates the internal circuitry that generates the reference voltages. the internal reference voltages are applied to the pins. good bypassing of the reference pins is critical to achieve optimum performance and is done by placing the bypass capacitors as close to the pins as possible. figure 12 shows the recommended bypass capacitor values. use high quality ceramic capacitors for the smaller values. avoid loading the internal reference with external circuitry. if the ADS1605/6 internal reference is to be used by other circuitry, buffer the reference voltages to prevent directly loading the reference pins. 10 f 22 f0.1 f 22 f 22 f 0.1 f 10 f 0.1 f 10 f 0.1 f 0.1 f ADS1605 ads1606 agnd vrefp vrefp vmid vcap vrefn vrefn figure 12. reference bypassing when using the internal reference external reference (refen = high) to use an external reference, set the refen pin high. this deactivates the internal generators for vrefp, vrefn and vmid, and saves approximately 25ma of current on the analog supply (avdd). the voltages applied to these pins must be within the values specified in the electrical characteristics table. t ypically vrefp = 4v , vmid = 2.5v and vrefn = 1v. the external circuitry must be capable of providing both a dc and a transient current. figure 13 shows a simplified diagram of the internal circuitry of the reference when the internal reference is disabled. as with the input circuitry, switches s1 and s2 open and close as shown in figure 9. s 1 ADS1605 ads1606 s 2 vrefp 50pf 300 ? s 1 vrefn vrefp vrefn figure 13. conceptual internal circuitry for the reference when refen = high figure 14 shows the recommended circuitry for driving these reference inputs. keep the resistances used in the buffer circuits low to prevent excessive thermal noise from degrading performance. layout of these circuits is critical, make sure to follow good high-speed layout practices. place the buffers and especially the bypass capacitors as close to the pins as possible. vcap is unaffected by the setting on refen and must be bypassed when using the internal or an external reference. 10 f 22 f 0.1 f 22 f 22 f 0.1 f 10 f 0.1 f 10 f 0.1 f 0.1 f vrefp vrefp vmid vcap vrefn vrefn 392 ? opa2822 ADS1605 ads1606 0.001 f 4v 392 ? opa2822 0.001 f 1v 392 ? opa2822 0.001 f 2.5v agnd figure 14. recommended buffer circuit when using an external reference
sbas274e ? march 2003 ? revised june 2004 www.ti.com 20 clock input (clk) the ADS1605/6 requires an external clock signal to be applied to the clk input pin. the sampling of the modulator is controlled by this clock signal. as with any high-speed data converter, a high quality clock is essential for optimum performance. crystal clock oscillators are the recommended clk source; other sources, such as frequency synthesizers are usually not adequate. make sure to avoid excess ringing on the clk input; keeping the trace as short as possible will help. measuring high frequency, large amplitude signals requires tight control of clock jitter. the uncertainty during sampling of the input from clock jitter limits the maximum achievable snr. this effect becomes more pronounced with higher frequency and larger magnitude inputs. fortunately, the ADS1605/6 oversampling topology reduces clock jitter sensitivity over that of nyquist rate converters like pipeline and successive approximation converters by a factor of 8 . in order to not limit the ADS1605/6 snr performance, keep the jitter on the clock source below the values shown in table 1. when measuring lower frequency and lower amplitude inputs, more clk jitter can be tolerated. in determining the allowable clock source jitter, select the worst-case input (highest frequency, largest amplitude) that will be seen in the application. table 1. maximum allowable clock source jitter for different input signal frequencies and amplitude input signal maximum allowable maximum frequency maximum amplitude allowable clock source jitter 2mhz ?2db 1.9ps 2mhz ?20db 14ps 1mhz ?2db 3.8ps 1mhz ?20db 28ps 500khz ?2db 7.6ps 500khz ?20db 57ps 100khz ?2db 38ps 100khz ?20db 285ps data format the 16-bit output data is in binary two?s complement format as shown in table 2. when the input is positive out-of-range, exceeding the positive full-scale value of 1.545v ref , the output clips to all 7fffh and the otr output goes high. likewise, when the input is negative out-of-range by going below the negative full-scale value of ?1.545v ref , the output clips to 8000h and the otr output goes high. the otr remains high while the input signal is out-of-range. table 2. output code versus input signal input signal (inp ? inn) ideal output code (1) otr +1.545v ref (> 0db) 7fff h 1 1.545v ref (0db) 7fff h 0 +1.545v ref 2 15 1 0001 h 0 0 0000 h 0 ?1.545v ref 2 15 1 ffff h 0 ?1.545v ref 2 15 2 15 1 8000 h 0 ?1.545v ref 2 15 2 15 1 8000 h 1 (1) excludes effects of noise, inl, offset and gain errors. out-of-range indication (otr) if the output code on dout[15:0] exceeds the positive or negative full-scale, the out-of-range digital output otr will go high on the falling edge of drdy . when the output code returns within the full-scale range, otr returns low on the falling edge of drdy . data retrieval data retrieval is controlled through a simple parallel interface. the falling edge of the drdy output indicates new data is available. to activate the output bus, both cs and rd must be low, as shown in table 3. make sure the dout bus does not drive heavy loads (> 20pf), as this will degrade performance. use an external buffer when driving an edge connector or cables. table 3. truth table for cs and rd cs rd dout[15:0] 0 0 active 0 1 high impedance 1 0 high impedance 1 1 high impedance
sbas274e ? march 2003 ? revised june 2004 www.ti.com 21 resetting the ADS1605 the ADS1605 and ads1606 with fifo disabled are asynchronously reset when the reset pin is taken low. during reset, all of the digital circuits are cleared, dout[15:0] are forced low, and drdy forced high. it is recommended that the reset pin be released on the falling edge of clk. afterwards, drdy goes low on the second rising edge of clk. allow 47 drdy cycles for the digital filter to settle before retrieving data. see figure 3 for the timing specifications. reset can be used to synchronize multiple ADS1605s. all devices to be synchronized must use a common clk input. with the clk inputs running, pulse reset on the falling edge of clk, as shown in figure 15. afterwards, the converters will be converting synchronously with the drdy outputs updating simultaneously. after synchronization, allow 47 drdy cycles (t 12 ) for output data to fully settle. reset ADS1605 1 clk drdy dout[15:0] drdy 1 dout[15:0] 1 reset clock reset ADS1605 2 clk drdy dout[15:0] drdy 2 dout[15:0] 2 clk reset drdy 1 dout[15:0] 1 synchronized settled data settled data drdy 2 dout[15:0] 2 t 12 figure 15. synchronizing multiple converters resetting the ads1606 the ads1606 with the fifo enabled requires a different reset sequence than the ADS1605, as shown in figure 16. ignore any drdy toggles that occur while reset is low. release reset on the rising edge of clk, then afterwards toggle rd to complete the reset sequence. toggle rd to complete reset sequence clk reset drdy r d t 26 ignore figure 16. resetting the ads1606 with the fifo enabled after resetting, the settling time for the ads1606 is 47 clk cycles, regardless of the fifo level. therefore, for higher fifo levels, it takes fewer drdy cycles to settle because the drdy period is longer. table 4 shows the number of drdy cycles required to settle for each fifo level. table 4. ads1606 reset settling fifo level filter settling time after reset (t 26 in units of drdy cycles ) 2 24 4 12 6 8 8 6 10 5 12 4 14 4
sbas274e ? march 2003 ? revised june 2004 www.ti.com 22 settling time the settling time is an important consideration when measuring signals with large steps or when using a multiplexer in front of the analog inputs. the ADS1605/6 digital filter requires time for an instantaneous change in signal level to propagate to the output. be sure to allow the filter time to settle after applying a large step in the input signal, switching the channel on a multiplexer placed in front of the inputs, resetting the ADS1605/6, or exiting the power-down mode, figure 17 shows the settling error as a function of time for a full-scale signal step applied at t = 0 with 2xmode = low. this figure uses drdy cycles (for the ADS1605 or the ads1606 with fifo disabled) for the time scale (x-axis). after 47 drdy cycles, the settling error drops below 0.001%. for f clk = 40mhz, this corresponds to a settling time of 9.4 s. 10 1 10 0 10 ? 1 10 ? 2 10 ? 3 10 ? 4 25 30 35 40 45 settling time (drdy cycles) settling error (%) 50 figure 17. settling time impulse response figure 18 plots the normalized response for an input applied at t = 0 with 2xmode = low . the x-axis units of time are drdy cycles (for the ADS1605 or the ads1606 with fifo disabled) . as shown in figure 18, the peak of the impulse takes 26 drdy cycles to propagate to the output. for f clk = 40mhz, a drdy cycle is 0.2 s in duration and the propagation time (or group delay) is 26 0.2 s = 5.2 s. 1.0 0.8 0.6 0.4 0.2 0 ? 0.2 ? 0.4 0 5 10 15 20 25 30 35 40 45 time (drdy cycles) normalized responce 50 figure 18. impulse response
sbas274e ? march 2003 ? revised june 2004 www.ti.com 23 frequency response the linear phase fir digital filter sets the overall frequency response. the decimation rate is set to 8 (2xmode = low) for all the figures shown in this section. figure 19 shows the frequency response from dc to 20mhz for f clk = 40mhz. the frequency response of the ADS1605/6 filter scales directly with clk frequency. for example, if the clk frequency is decreased by half (to 20mhz), the values on the x-axis in figure 19 would need to be scaled by half, with the span becoming dc to 10mhz. figure 20 shows the passband ripple from dc to 2.2mhz (f clk = 40mhz). figure 21 shows a closer view of the passband transition by plotting the response from 2.0mhz to 2.5mhz (f clk = 40mhz). the overall frequency response repeats at multiples of the clk frequency. to help illustrate this, figure 22 shows the response out to 120mhz (f clk = 40mhz). notice how the passband response repeats at 40mhz, 80mhz and 120mhz; it is important to consider this when there is high-frequency noise present with the signal. the modulator bandwidth extends to 100mhz. high-frequency noise around 40mhz and 80mhz will not be attenuated by either the modulator or the digital filter. this noise will alias back in-band and reduce the overall snr performance unless it is filtered out prior to the ADS1605/6. to prevent this, place an anti-alias filter in front of the ADS1605/6 that rolls off before 37mhz. 20 0 ? 20 ? 40 ? 60 ? 80 ? 100 ? 120 04 2 6 10 14 18 8 frequency (mhz) 12 16 20 magnitude (db) f clk =40mhz figure 19. frequency response. 0.0025 0.0020 0.0015 0.0010 0.0005 0 ? 0.0005 ? 0.0010 ? 0.0015 ? 0.0020 00.51.0 frequency (mhz) 1.5 2.0 2.5 magnitude (db) f clk =40mhz figure 20. passband ripple 1 0 ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 7 2.0 2.1 2.05 2.15 2.25 2.35 2.45 2.2 frequency (mhz) 2.3 2.4 2.5 magnitude (db) f clk =40mhz figure 21. passband transition 20 0 ? 20 ? 40 ? 60 ? 80 ? 100 02040 frequency (mhz) 60 80 120 100 magnitude (db) f clk = 40mhz figure 22. frequency response out to 120mhz
sbas274e ? march 2003 ? revised june 2004 www.ti.com 24 fifo (ads1606 only) the ads1606 includes an adjustable level first-in first-out buffer (fifo) for the output data. the fifo allows data to be temporarily stored within the ads1606 to provide more flexibility for the host controller when retrieving data. pins fifo_lev[2:0] set the level or depth of the fifo. note that these pins must be left unconnected on the ADS1605. the fifo is enabled by setting at least one of the fifo_lev inputs high. table 5 shows the corresponding fifo level and drdy period for the different combinations of fifo_lev[2:0] settings. for the best performance when using the fifo, it is recommended to: 1. set iovdd = 3v. 2. synchronize data retrieval with clk. 3. minimize loading on outputs dout[15:0]. 4. ensure rise and fall times on clk and rd are 1ns or longer. table 5. fifo buffer level settings for the ads1606 fifo_lev[2:0] fifo buffer level drdy period 000 0: disabled, operates like ADS1605 8/f clk 001 2 16/f clk 010 4 32/f clk 011 6 48/f clk 100 8 64/f clk 101 10 80/f clk 110 12 96/f clk 111 14 112/f clk fifo operation the ads1606 fifo collects the number of output readings set by the level corresponding to the fifo_lev[2:0] setting. when the specified level is reached, drdy is pulsed high, indicating the data in the fifo is ready to be read. the drdy period is a function of the fifo level, as shown in table 5. to read the data, make sure cs is low (it is acceptable to tie it low) and then take rd low. the first, or oldest, data will be presented on the data output pins. after reading this data, advance to the next data reading by toggling rd . on the next falling edge of rd , the second data is present on the data output pins. continue this way until all the data have been read from the fifo, making sure to take rd high when complete. afterwards, wait until drdy toggles and repeat the readback cycle. figure 23 shows an example readback when fifo_lev[2:0] = 010 (level = 4). readback considerations the exact number of data readings set by the fifo level must be read back each time drdy toggles. the one exception is that readback can be skipped entirely. in this case, the drdy period increases to 128 clk period. figure 24 shows an example when readback is skipped with the fifo level = 4. do not read back more or less readings from the fifo than set by the level. this interrupts the fifo operation and can cause drdy to stay low indefinitely. if this occurs, the reset pin must be toggled followed by a rd pulse. this resets the ads1606 fifo and also the digital filter, which then must settle afterwards before valid data is ready. see the section, resetting the ads1606 , for more details. setting the fifo level the fifo level setting is usually a static selection that is set when power is first applied to the ads1606. if the fifo level needs to be changed after powerup, there are two options. one is to asynchronously set the new value on pin fifo_lev[2:0] then toggle reset . remember that the ads1606 will need to settle after resetting. see the section, resetting the ads1606 , for more details. the other option avoids requiring a reset, but needs synchronization of the fifo level change with the readback. the fifo_lev[2:0] pins have to be changed after rd goes high after reading the first data, but before rd goes low to read the last data from the fifo. the new fifo level becomes active immediately and the drdy period adjusts accordingly. when decreasing the fifo level this way, make sure to give adequate time for readback of the data before setting the new, smaller level. figure 25 shows an example of a synchronized fifo level change from 4 to 8. drdy dout[15:0] (1) cs can be tied low. (2) data 1 is the oldest data and data 4 is the most recent. cs (1) rd data 1 (2) data 2 data 3 data 4 figure 23. example of fifo readback when fifo level = 4
sbas274e ? march 2003 ? revised june 2004 www.ti.com 25 32/f clk 128/f clk drdy rd figure 24. example of skipping readback when fifo level = 4 64/f clk drdy fifo_lev[2:0] 010 (level = 4) change fifo_lev[2:0] here 100 (level = 8) rd 32/f clk figure 25. example of synchronized change of fifo level from 4 to 8 analog power dissipation an external resistor connected between the rbias pin and the analog ground sets the analog current level, as shown in figure 26. the current is inversely proportional to the resistor value. table 6 shows the recommended values of r bias for different clk frequencies. notice that the analog current can be reduced when using a slower frequency clk input because the modulator has more time to settle. avoid adding any capacitance in parallel to r bias , since this will interfere with the internal circuitry used to set the biasing. r bias rbias agnd ads1606 ADS1605 figure 26. external resistor used to set analog power dissipation table 6. recommended r bias resistor values for different clk frequencies f clk data rate r bias typical power dissipation with refen high 16mhz 2mhz 60k ? 315mw 24mhz 3mhz 50k ? 400mw 32mhz 4mhz 45k ? 475mw 40mhz 5mhz 37k ? 570mw power down (pd ) when not in use, the ADS1605/6 can be powered down by taking the pd pin low. all circuitry will be shutdown, including the voltage reference. to minimize the digital current during power down, stop the clock signal supplied to the clk input. there is an internal pull-up resistor of 170k ? on the pd pin, but it is recommended that this pin be connected to iovdd if not used. if using the ads1606 with the fifo enabled, issue a reset after exiting power-down mode. make sure to allow time for the reference to start up after exiting power-down mode. the internal reference typically requires 15ms. after the reference has stabilized, allow at least 100 drdy cycles for the modulator and digital filter to settle before retrieving data.
sbas274e ? march 2003 ? revised june 2004 www.ti.com 26 power supplies three supplies are used on the ADS1605/6: analog (avdd), digital (dvdd) and digital i/o (iovdd). each supply must be suitably bypassed to achieve the best performance. it is recommended that a 1 f and 0.1 f ceramic capacitor be placed as close to each supply pin as possible. connect each supply-pin bypass capacitor to the associated ground, as shown in figure 27. each main supply bus should also be bypassed with a bank of capacitors from 47 f to 0.1 f, as shown. the io and digital supplies (iovdd and dvdd) can be connected together when using the same voltage. in this case, only one bank of 47 f to 0.1 f capacitors is needed on the main supply bus, though each supply pin must still be bypassed with a 1 f and 0.1 f ceramic capacitor. c p c p c p c p c p c p c p c p 1 2 3 9 10 11 12 18 58 57 55 54 53 52 51 19 25 26 avdd avdd agnd agnd c p 6 7 avdd agnd agnd avdd 47 f 47 f 47 f4.7 f1 f0.1 f 0.1 f 0.1 f 1 f 1 f 4.7 f 4.7 f dvdd avdd agnd agnd dgnd iovdd dvdd dgnd dgnd dgnd dvdd ADS1605 ads1606 if using separate analog and digital ground planes, connect together on the ADS1605/6 pcb. dgnd note: c p =1 f ?? 0.1 f agnd avdd iovdd dvdd figure 27. recommended power-supply bypassing
sbas274e ? march 2003 ? revised june 2004 www.ti.com 27 2x mode the 2xmode digital input determines the performance (16-bit or 14-bit) by setting the oversampling ratio. when 2xmode = low, the oversampling ratio = 8 for 16-bit performance. when 2xmode = high, the oversampling ratio = 4 for 14-bit performance. note that when 2xmode is high, all 16 bits of dout remain active. decreasing the oversampling ratio from 8 to 4 doubles the data rate in 2x mode. for f clk = 40mhz, the data rate then becomes 10msps. in addition, the group delay decreases to 0.9 s and the settling time becomes 1.3 s or 13 drdy cycles. with the reduced oversampling in 2x mode, the noise increases. typical snr performance degrades by 14db. thd remains approximately the same. there is an internal pull-down resistor of 170k ? on the 2xmode, however, it is recommended this pin be forced either high or low. for more information on the performance of the 2x mode, see application note operating the ADS1605 and ads1606 in 2x mode: 10msps (slaa180), available for download at www.ti.com. layout issues the ADS1605/6 is a very high-speed, high-resolution data converter. in order to achieve the maximum performance, careful attention must be given to the printed circuit board (pcb) layout. use good high-speed techniques for all circuitry. critical capacitors should be placed close to pins as possible. these include capacitors directly connected to the analog and reference inputs and the power supplies. make sure to also properly bypass all circuitry driving the inputs and references. two approaches can be used for the ground planes: either a single common plane; or two separate planes, one for the analog grounds and one for the digital grounds. when using only one common plane, isolate the flow of current on pin 57 from pin 1; use breaks on the ground plane to accomplish this. pin 57 carries the switching current from the analog clocking for the modulator and can corrupt the quiet analog ground on pin 1. when using two planes, it is recommended that they be tied together right at the pcb. do not try to connect the ground planes together after running separately through edge connectors or cables as this reduces performance and increases the likelihood of latchup. in general, keep the resistances used in the driving circuits for the inputs and reference low to prevent excess thermal noise from degrading overall performance. avoid having the ADS1605/6 digital outputs drive heavy loads. buffers on the outputs are recommended unless the ADS1605/6 is connected directly to a dsp or controller situated nearby. additionally, make sure the digital inputs are driven with clean signals as ringing on the inputs can introduce noise. the ADS1605/6 uses ti powerpad technology. the powerpad is physically connected to the substrate of the silicon inside the package and must be soldered to the analog ground plane on the pcb using the exposed metal pad underneath the package for proper heat dissipation. please refer to application report slma002, located at www.ti.com, for more details on the powerpad package.
sbas274e ? march 2003 ? revised june 2004 www.ti.com 28 applications information interfacing the ADS1605 to the tms320c6000 figure 28 illustrates how to directly connect the ADS1605 to the tms320c6000 dsp. the processor controls reading using output are . the ADS1605 is selected using the dsp control output, ce2 . the ADS1605 16-bit data output bus is directly connected to the tms320c6000 data bus. the data ready output from the ADS1605, drdy , drives interrupt ext_int7 on the tms320c6000. dout[15:0] ADS1605 drdy cs 16 rd xd[15:0] tms320c6000 ext_int7 ce2 are figure 28. ADS1605?tms320c6000 interface connection interfacing the ads1606 to the tms320c6000 figure 29 illustrates how to directly connect the ads1606 to the tms320c6000 dsp. the processor controls reading using output are . the ads1606 is permanently selected by grounding the cs pin. the ads1606 16-bit data output bus is directly connected to the tms320c6000 data bus. the data ready output from the ads1606, drdy , drives interrupt ext_int7 on the tms320c6000. dout[15:0] ads1606 drdy cs 16 rd xd[15:0] tms320c6000 ext_int7 are figure 29. ads1606?tms320c6000 interface connection
sbas274e ? march 2003 ? revised june 2004 www.ti.com 29 interfacing the ADS1605 to the tms320c5400 figure 30 illustrates how to connect the ADS1605 to the tms320c5400 dsp. the processor controls the reading using the outputs r/w and is . the i/o space select signal (is ) is optional and is used to prevent the ADS1605 rd input from being strobed when the dsp is accessing other external memory spaces (address or data). this can help reduce the possibility of digital noise coupling into the ADS1605. when not using this signal, replace nand gate u1 with an inverter between r/w and rd . two signals, iostrb and a15, combine using nand gate u2 to select the ADS1605. if there are no additional devices connected to the tms320c5400 i/o space, u2 can be eliminated. simply connect iostrb directly to cs . the ADS1605 16-bit data output bus is directly connected to the tms320c5400 data bus. the data ready output from the ADS1605, drdy , drives interrupt int3 on the tms320c5400. dout[15:0] ADS1605 drdy cs 16 rd d[15:0] tms320c5400 int3 iostrb r/w a15 is u1 u2 figure 30. ADS1605?tms320c5400 interface connection interfacing the ads1606 to the tms320c5400 figure 31 illustrates how to directly connect the ads1606 to the tms320c5400 dsp. the processor controls reading using outputs r/w and is . the ads1606 is permanently selected by grounding the cs pin. if there are any additional devices connected to thetms320c5400 i/o space, address decode logic will be required between the adc and the dsp to prevent data bus contention and ensure only one device at a time is selected. the ads1606 16-bit data output bus is directly connected to the tms320c5400 data bus. the data ready output from the ads1606, drdy , drives interrupt int3 on the tms320c5400. dout[15:0] ads1606 drdy cs 16 rd d[15:0] tms320c5400 int3 r/w is u1 figure 31. ads1606?tms320c5400 interface connection code composer studio, available from ti, provides support for interfacing ti dsps through a collection of data converter plugins. check the ti website, located at www.ti.com/sc/dcplug?in, for the latest information on ADS1605/6 support.
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) ADS1605ipapr active htqfp pap 64 1000 none cu nipdau level-3-235c-168 hr ADS1605ipapt active htqfp pap 64 250 none cu nipdau level-3-235c-168 hr ads1606ipapr active htqfp pap 64 1000 none cu nipdau level-3-235c-168 hr ads1606ipapt active htqfp pap 64 250 none cu nipdau level-3-235c-168 hr (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - may not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. none: not yet available lead (pb-free). pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. green (rohs & no sb/br): ti defines "green" to mean "pb-free" and in addition, uses package materials that do not contain halogens, including bromine (br) or antimony (sb) above 0.1% of total product weight. (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedecindustry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 18-feb-2005 addendum-page 1

important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband interface interface.ti.com digital control www.ti.com/digitalcontrol logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security telephony www.ti.com/telephony video & imaging www.ti.com/video wireless www.ti.com/wireless mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2005, texas instruments incorporated

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